HP Labs Fellow Presents the “Nanostore” (from the UK Register)

HP Labs has announced packing layers of RAM, caches and storage into a combined block of memristors and processor cores to create highly scalable “nanostore” systems. HP Labs Fellow Parthasarathy Ranganathan presented the blueprints at the San Jose Server Design Summit this week, according to EE Times.

“The key property of nanostores is the colocation of processors with nonvolatile storage, eliminating many intervening levels of the storage hierarchy. All data is stored in a single-level nonvolatile memory datastore that replaces traditional disk and DRAM layers – disk use is relegated to archival backups.

A single nanostore chip consists of multiple 3D-stacked layers of dense silicon nonvolatile memories, such as phase change memories or memristors, with a top layer of power-efficient compute cores. Through-silicon vias are used to provide wide low-energy datapaths between the processors and the datastores.

Each nanostore can act as a full-fledged system with a network interface. Individual such nanostores are networked through onboard connectors to form a large-scale distributed system or cluster akin to current large-scale clusters for data-centric computing. The system can support different network topologies, including traditional fat trees or recent proposals like HyperX.”

More (including downloadable paper) at http://www.theregister.co.uk/2012/11/29/hp_nanostore/

One thought on “HP Labs Fellow Presents the “Nanostore” (from the UK Register)

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